ULSI Process Integration III: Proceedings of the International SymposiumThe Electrochemical Society, 2003 - 598 էջ |
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Common terms and phrases
achieved active addition annealing applications barrier body bulk capacitance capacitor cell channel characteristics charge circuit CMOS compared concentration conventional crystal defect density dependence deposition developed devices dielectric diffusion discussed distribution doping drain DRAM effect electrical Electron energy etching fabrication Figure film flow followed formation formed frequency gate higher hole IEEE implantation important improved increase integration interconnect interface introduced isolation junction layer leakage length limited lithography lower material measured memory metal mobility MOSFET needed nitride node obtained operation oxide parameters particles performance Phys poly potential present production reduced region reliability removal reported resistance scaling semiconductor shift shown in Fig shows SiGe silicon simulation single SiO2 step stress structure substrate surface techniques temperature thermal thickness thin threshold voltage transistor trench values voltage wafer
Սիրված հատվածներ
Էջ 388 - L. Manchanda, ML Green, RB van Dover, MD Morris, A. Kerber, Y. Hu, J.-P. Han, PJ Silverman, TW Sorsch, G. Weber, V. Donnelly, K. Pelhos, F. Klemens, NA Ciampa, A. Kornblit, YO Kim, JE Bower, D. Barr, E. Ferry, D. Jacobson, J. Eng, B. Busch, and H. Schulte, "Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a Novel gate dielectric for low power applications,
Էջ 503 - SON process [14], the silicon film and buried insulator, both of nanometric scale, are defined by epitaxy on a bulk substrate. Therefore, the SON process opens access to extremely thin films (the Silicon channel as well as the BOX) at the same time offering the thickness control as fine as the resolution of the epi process (less than Inm).
Էջ 205 - A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation", IEEE Trans.
Էջ 39 - With the advent of the transistor and the work in semiconductors generally, it seems now possible to envisage electronic equipment in a solid block with no connecting wires. The block may consist of layers of insulating, conducting, rectifying and amplifying materials, the electrical functions being connected directly by cutting out areas of the various layers.
Էջ 62 - EH Snow, AS Grove, BE Deal, and CT Sah, "Ion Transport Phenomena in Insulating Films,
Էջ 66 - JR Brews, W. Fichtner, EH Nicollian, and SM Sze, "Generalized guide for MOSFET miniaturization," IEEE Electron Device Lett., vol.
Էջ 67 - GD Wilk, RM Wallace, and JM Anthony, "High-k gate dielectrics: Current status and materials properties considerations", J.
Էջ 236 - Y. Taur, DA Buchanan, W. Chen, DJ Frank, KE Ismail, SH Lo, GA Sai-Halasz, RG Viswanathan. HJC Wann, SJ Wind, and HS Wong, "CMOS scaling into the nanometer regime,
Էջ 56 - W. Shockley, GL Pearson, and JR Haynes, "Hole Injection in Germanium — Quantitative Studies and Filamentary Transistors,
Էջ 17 - I reasoned that polycrystalline germanium, with its variations in resistivity and its randomly occurring grain boundaries, twins and crystal defects that acted as uncontrolled resistances, electron or hole emitters and traps would affect transistor operation in uncontrolled ways.